ASP-DAC 2009:
Yokohama,
Japan
Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009.
IEEE 2009, ISBN 978-1-4244-2748-2 
- Mitsuo Saito:
Challenges to EDA system from the view point of processor design and technology drivers.
- Wolfgang Rosenstiel:
Automated synthesis and verification of embedded systems: wishful thinking or reality?
- Leon Stok:
From restrictive to prescriptive design.
On-chip communication architectures
- Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang:
Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures.
1-6
- Yue Qian, Zhonghai Lu, Wenhua Dou:
Analysis of communication delay bounds for network on chips.
7-12
- Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Jun Yang, Li Zhao:
Frequent value compression in packet-based NoC architectures.
13-18
- Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang:
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture.
19-24
- Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi:
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.
25-30
Dealing with thermal issues
- Pei-Yu Huang, Jia-Hong Wu, Yu-Min Lee:
Stochastic thermal simulation considering spatial correlated within-die process variations.
31-36
- Francesco Zanini, David Atienza, Giovanni De Micheli:
A control theory approach for thermal balancing of MPSoC.
37-42
- Michael B. Healy, Hsien-Hsin S. Lee, Gabriel H. Loh, Sung Kyu Lim:
Thermal optimization in multi-granularity multi-core floorplanning.
43-48
- Yu-Wei Yang, Katherine Shu-Min Li:
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement.
49-54
- Shih-An Yu, Pei-Yu Huang, Yu-Min Lee:
A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects.
55-60
Advances in behavioral synthesis
University LSI design contest
- Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda:
A wireless real-time on-chip bus trace system.
91-92
- Chin-Hsien Wang, Ching-Hwa Cheng, Jiun-In Guo:
CKVdd: a self-stabilization ramp-vdd technique for dynamic power reduction.
93-94
- Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya:
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.
95-96
- Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai:
A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver.
97-98
- Ahmet Oncu, Minoru Fujishima:
Low-power CMOS transceiver circuits for 60GHz band millimeter-wave impulse radio.
99-100
- Hui Shao, Chi-Ying Tsui, Wing-Hung Ki:
An inductor-less MPPT design for light energy harvesting systems.
101-102
- Xiaolei Zhu, Sanroku Tsukamoto, Tadahiro Kuroda:
A 1 GHz CMOS comparator with dynamic offset control technique.
103-104
- Keita Ikai, Jinmyoung Kim, Makoto Ikeda, Kunihiro Asada:
Circuit design using stripe-shaped PMELA TFTs on glass.
105-106
- Hui Shao, Chi-Ying Tsui:
Low energy level converter design for sub-Vth logics.
107-108
- Kazuya Shimizu, Masato Kaneta, HaiJun Lin, Haruo Kobayashi, Nobukazu Takai, Masao Hotta:
A Time-to-Digital Converter with small circuitry.
109-110
- H. Oshiyama, T. Matsuda, K. Suzuki, Hideyuki Iwata, Takashi Ohzone:
A VDD independent temperature sensor circuit with scaled CMOS process.
111-112
- Chihiro Kawabata, Yasuhiro Sugimoto:
A current-mode DC-DC converter using a quadratic slope compensation scheme.
113-114
- Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu:
Ultra low-power ANSI S1.11 filter bank for digital hearing aids.
115-116
- Daisaku Seto, Minoru Watanabe:
An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture.
117-118
- Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A low-power FPGA based on autonomous fine-grain power-gating.
119-120
- Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, An-Yeu Wu:
A 52-mW 8.29mm2 19-mode LDPC decoder chip for mobile WiMAX applications.
121-122
- Ming-Chien Tsai, Ching-Hwa Cheng:
A full-synthesizable high-precision built-in delay time measurement circuit.
123-124
- Hsiu-Cheng Chang, Yao-Chang Yang, Jia-Wei Chen, Ching-Lung Su, Cheng-An Chien, Jiun-In Guo, Jinn-Shyan Wang:
A dynamic quality-scalable H.264 video encoder chip.
125-126
- Wen Ji, Yuta Abe, Takeshi Ikenaga, Satoshi Goto:
A high performance LDPC decoder for IEEE802.11n standard.
127-128
- Masa-Aki Fukase, Kazunori Noda, Atsuko Yokoyama, Tomoaki Sato:
Design and chip implementation of the ubiquitous processor HCgorilla.
129-130
- Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang:
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.
131-132
- Dan Cao, Jun Han, Xiaoyang Zeng, Shi-ting Lu:
A multi-task-oriented security processing architecture with powerful extensibility.
133-134
- Wu Fang, Zhang Huowen, Duan Lei, Lai Jinmei, Wang Yuan, Tong Jiarong:
A delay-optimized universal FPGA routing architecture.
135-136
MPSoC and IP integration
Power analysis and optimization
- Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong:
Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.
161-166
- Jason Cong, Puneet Gupta, John Lee:
On the futility of statistical power optimization.
167-172
- Shih-Hsu Huang, Chun-Hua Cheng:
Timing driven power gating in high-level synthesis.
173-178
- Pingqiang Zhou, Karthikk Sridharan, Sachin S. Sapatnekar:
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors.
179-184
- Yiyu Shi, Wei Yao, Jinjun Xiong, Lei He:
Incremental and on-demand random walk for iterative power distribution network analysis.
185-190
Logic and arithmetic optimization
- Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang:
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique.
191-196
- F. S. Chim, T. K. Lam, Y. L. Wu:
On improved scheme for digital circuit rewiring and application on further improving FPGA technology mapping.
197-202
- Amit Verma, Ajay K. Verma, Philip Brisk, Paolo Ienne:
Hybrid LZA: a near optimal implementation of the leading zero anticipator.
203-209
- P. K. Meher, Yajun Ha, Chiou-Yng Lee:
An optimized design for serial-parallel finite field multiplication over GF(2m) based on all-one polynomials.
210-215
EDA acceleration using new architectures
System-level design of 3D chips and configurable systems
- Xiangyu Dong, Yuan Xie:
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs).
234-241
- Srinivasan Murali, Ciprian Seiculescu, Luca Benini, Giovanni De Micheli:
Synthesis of networks on chips for 3D systems on chips.
242-247
- Fabio Cancare, Marco D. Santambrogio, Donatella Sciuto:
An application-centered design flow for self reconfigurable systems implementation.
248-253
- Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Francky Catthoor:
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.
254-259
Advances in timing analysis and modeling
- Kanupriya Gulati, Sunil P. Khatri:
Accelerating statistical static timing analysis using graphics processing units.
260-265
- Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Trade-off analysis between timing error rate and power dissipation for adaptive speed control with timing error prediction.
266-271
- Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng:
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.
272-277
- Lin Xie, Azadeh Davoodi:
Bound-based identification of timing-violating paths under variability.
278-283
- Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar:
Adaptive techniques for overcoming performance degradation due to aging in digital circuits.
284-289
Hardware dependent software for multi- and many-core embedded systems
- Rainer Dömer, Andreas Gerstlauer, Wolfgang Müller:
Introduction to hardware-dependent software design hardware-dependent software for multi- and many-core embedded systems.
290-292
- Wolfgang Ecker, Stefan Heinen, Michael Velten:
Using a dataflow abstracted virtual prototype for HdS-design.
293-300
- Yasutaka Tsunakawa:
Needs and trends in embedded software development for consumer electronics.
301-303
- Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Lo Chi Yu Lo, Daniel Gajski:
Hardware-dependent software synthesis for many-core embedded systems.
304-310
System level architectures
- Cathy Qun Xu, Chun Jason Xue, Bessie C. Hu, Edwin Hsing-Mean Sha:
Computation and data transfer co-scheduling for interconnection bus minimization.
311-316
- Antonino Tumeo, Marco Branca, Lorenzo Camerini, Marco Ceriani, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.
317-322
- Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
Variability-aware robust design space exploration of chip multiprocessor architectures.
323-328
- Young-Su Kwon, Bontae Koo, Nak-Woong Eum:
Partial conflict-relieving programmable address shuffler for parallel memories in multi-core processor.
329-334
- Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic:
HitME: low power Hit MEmory buffer for embedded systems.
335-340
Beyond traditional floorplanning and placement
Signal/power integrity and simulation
- Yiyu Shi, Jinjun Xiong, Howard Chen, Lei He:
Stochastic current prediction enabled frequency actuator for runtime resonance noise reduction.
373-378
- Hai Wang, Hao Yu, Sheldon X.-D. Tan:
Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.
379-384
- Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng:
High performance on-chip differential signaling using passive compensation for global communication.
385-390
- Wanping Zhang, Yi Zhu, Wenjian Yu, Amirali Shayan Arani, Renshen Wang, Zhi Zhu, Chung-Kuan Cheng:
Noise minimization during power-up stage for a multi-domain power network.
391-396
- He Peng, Chung-Kuan Cheng:
Parallel transistor level circuit simulation using domain decomposition methods.
397-402
- Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry:
Fast circuit simulation on graphics processing units.
403-408
Challenges in 3D integrated circuit design
Energy-aware system level design methodology
- Florin Balasa, Ilie I. Luican, Hongwei Zhu, Doru V. Nasui:
System-level exploration tool for energy-aware memory management in the design of multidimensional signal processing systems.
443-448
- Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
449-454
- Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan:
A framework for estimating NBTI degradation of microarchitectural components.
455-460
Design for manufacturing and reliability
Analog,
RF and mixed-signal CAD
- Yu Liu, Masato Yoshioka, Katsumi Homma, Toshiyuki Shibuya:
Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuit.
498-503
- Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil:
Automated design and optimization of circuits in emerging technologies.
504-509
- Samiran DasGupta, Pradip Mandal:
An automated design approach for CMOS LDO regulators.
510-515
- Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu:
A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level.
516-521
- Prateek Bhansali, Jaijeet S. Roychowdhury:
Gen-Adler: the Generalized Adler's equation for injection locking analysis in oscillators.
522-527
Designers' forum:
consumer SoC
- Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa, Toru Fujihira, Kenichi Iwata, Motoki Kimura, Fumitaka Izuhara, Seiji Mochizuki, Masaki Nobori:
Development of full-HD multi-standard video CODEC IP based on heterogeneous multiprocessor architecture.
528-534
- Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka:
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management.
535-539
- Yoshito Nishimichi, Nobuo Higaki, Masataka Osaka, Seiji Horii, Hisato Yoshida:
UniPhier: series development and SoC management.
540-545
System level simulation and modeling
- Aimen Bouchhima, Patrice Gerin, Frédéric Pétrot:
Automatic instrumentation of embedded software for high level hardware/software co-simulation.
546-551
- Eric Cheung, Harry Hsieh, Felice Balarin:
Fast and accurate performance simulation of embedded software for MPSoC.
552-557
- Chen Kang Lo, Ren-Song Tsay:
Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model.
558-563
- Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami:
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.
564-569
Chip and package routing techniques
- Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li:
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.
570-575
- Yue Xu, Yanheng Zhang, Chris Chu:
FastRoute 4.0: global router with efficient via minimization.
576-581
- Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang:
High-performance global routing with fast overflow reduction.
582-587
- Jin-Tai Yan, Zhi-Wei Chen:
IO connection assignment and RDL routing for flip-chip designs.
588-593
- Lijuan Luo, Martin D. F. Wong:
On using SAT to ordered escape problems.
594-599
- Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi:
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound.
600-605
Compilation techniques for embedded systems
Sequential design verification
Scan test generation
- Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara:
Fast false path identification based on functional unsensitizability using RTL information.
660-665
- Zhen Chen, Boxue Yin, Dong Xiang:
Conflict driven scan chain configuration for high transition fault coverage and low test power.
666-671
- Irith Pomeranz, Sudhakar M. Reddy:
Dynamic test compaction for a random test generation procedure with input cube avoidance.
672-677
- Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detectability of internal bridging faults in scan chains.
678-683
- Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu:
Fault modeling and testing of retention flip-flops in low power designs.
684-689
Designers' forum:
analog/RF circuit designs
- Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho:
Design methods for pipeline & delta-sigma A-to-D converters with convex optimization.
690-695
- Takashi Kawamoto, Masaru Kokubo:
A low-jitter 1.5-GHz and large-EMI reduction 10-dBm spread-spectrum clock generator for Serial-ATA.
696-701
- Nobuyuki Itoh, Mototsugu Hamada:
RF-analog circuit design in scaled SoC.
702-707
- Yuichi Kado, Mitsuru Harada:
An approach to the RF-LSI design for ubiquitous communication appliances.
708-714
High-level design and scheduling
Emerging design methodologies and applications
- Yexin Zheng, Chao Huang:
A novel Toffoli network synthesis algorithm for reversible logic.
739-744
- Zahra Sasanian, Mehdi Saeedi, Mehdi Sedighi, Morteza Saheb Zamani:
A cycle-based synthesis algorithm for reversible logic.
745-750
- Pankaj Bhagawat, Rajballav Dash, Gwan S. Choi:
Array like runtime reconfigurable MIMO detectors for 802.11n WLAN: a design case study.
751-756
- Akira Kuroda, Mayuko Koezuka, Hidenori Matsuzaki, Takashi Yoshikawa, Shigehiro Asano:
Mapping method for dynamically reconfigurable architecture.
757-762
- Srinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan:
A criticality-driven microarchitectural three dimensional (3D) floorplanner.
763-768
Verification,
test,
and yield
- Shujun Deng, Zhiqiu Kong, Jinian Bian, Yanni Zhao:
Self-adjusting constrained random stimulus generation using splitting evenness evaluation and XOR constraints.
769-774
- Xuan-Lun Huang, Chen-Yuan Yang, Jiun-Lang Huang:
Diagnosing integrator leakage of single-bit first-order DeltaSigma modulator using DC input.
775-780
- Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum:
Path selection for monitoring unexpected systematic timing effects.
781-786
- Mesut Meterelliyoz, Kaushik Roy:
Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.
787-792
- Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara:
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.
793-798
Memory systems simulation and optimization
- Li-Pin Chang, Chen-Hui Hsu:
Soft lists: a native index structure for NOR-flash-based embedded devices.
799-804
- Yingchao Zhao, Chun Jason Xue, Minming Li, Bessie C. Hu:
Energy-aware register file re-partitioning for clustered VLIW architectures.
805-810
- Eric Cheung, Harry Hsieh, Felice Balarin:
Memory subsystem simulation in software TLM/T models.
811-816
- Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Exact and fast L1 cache simulation for embedded systems.
817-822
- Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay:
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications.
823-828
Emerging technologies
- Seid Hadi Rasouli, Hanpei Koike, Kaustav Banerjee:
High-speed low-power FinFET based domino logic.
829-834
- M. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli:
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.
835-840
- Jing Li, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy:
An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.
841-846
- Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy:
A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems.
847-852
- Bao Liu:
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture.
853-858
Dependable VLSI:
device,
design and architecture---how should they cooperate?
Copyright © Mon Nov 2 20:20:53 2009
by Michael Ley (ley@uni-trier.de)
