PACT 2004: Antibes Juan-les-Pins, France

Session 1: Code Generation

• Cédric Bastoul:
  Code Generation in the Polyhedral Model Is Easier Than You Think. 7-16
  
• Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai:
  A Compiler Framework for Recovery Code Generation in General Speculative Optimizations. 17-28
  
• Yuri Dotsenko, Cristian Coarfa, John M. Mellor-Crummey:
  A Multi-Platform Co-Array Fortran Compiler. 29-40
  
• M. Anton Ertl, David Gregg:
  Retargeting JIT Compilers by using C-Compiler Generated Executable Code. 41-50
  

Session 2: Architecture

• Marc Epalza, Paolo Ienne, Daniel Mlynek:
  Adding Limited Reconfigurability to Superscalar Processors. 53-62
  
• Alex Settle, Joshua L. Kihm, Andrew Janiszewski, Daniel A. Connors:
  Architectural Support for Enhanced SMT Job Scheduling. 63-73
  
• Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler:
  Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures. 74-84
  
• Leonardo R. Bachega, Siddhartha Chatterjee, Kenneth A. Dockser, John A. Gunnels, Manish Gupta, Fred G. Gustavson, Christopher A. Lapkowski, Gary K. Liu, Mark P. Mendell, Charles D. Wait, T. J. Christopher Ward:
  A High-Performance SIMD Floating Point Unit for BlueGene/L: Architecture, Compilation, and Algorithm Design. 85-96
  

Session 3: Memory Hierarchy

• Tulika Mitra, Abhik Roychoudhury, Qinghua Shen:
  Impact of Java Memory Model on Out-of-Order Multiprocessors. 99-110
  
• Seongbeom Kim, Dhruba Chandra, Yan Solihin:
  Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture. 111-122
  
• Weidong Shi, Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu:
  Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. 123-134
  
• Kyle J. Nesbit, Ashutosh S. Dhodapkar, James E. Smith:
  AC/DC: An Adaptive Data Cache Prefetcher. 135-145
  

Keynote Address

• Tadashi Watanabe:
  The Earth Simulator and Beyond-Technological Considerations Toward the Sustained PetaFlops Machine. 149-
  

Session 4: Compiler Optimizations

• YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi:
  The Energy Impact of Aggressive Loop Fusion. 153-164
  
• Dhruva R. Chakrabarti, Luis A. Lozano, Xinliang D. Li, Robert Hundt, Shin-Ming Liu:
  Scalable High Performance Cross-Module Inlining. 165-176
  
• Ram Rangan, Neil Vachharajani, Manish Vachharajani, David I. August:
  Decoupled Software Pipelining with the Synchronization Array. 177-188
  
• Wen Xu, Sanjeev Kumar, Kai Li:
  Fast Paths in Concurrent Programs. 189-200
  

Session 5: Parallel Systems

• Jialin Dou, Marcelo H. Cintra:
  Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization. 203-214
  
• Gladys Utrera, Julita Corbalán, Jesús Labarta:
  Implementing Malleability on MPI Jobs. 215-224
  
• Michael Ball, Cristina Cifuentes, Deepankar Bairagi:
  Partitioning of Code for a Massively Parallel Machine. 225-236
  

Keynote Address

• Stamatis Vassiliadis:
  Polymorphic Processors: How to Expose Arbitrary Hardware Functionality to Programmers. 239-
  

Session 6: Memory Parallelism

• Silvius Rus, Dongmin Zhang, Lawrence Rauchwerger:
  The Value Evolution Graph and its Use in Memory Reference Analysis. 243-254
  
• Takeshi Ogasawara, Hideaki Komatsu, Toshio Nakatani:
  TO-Lock: Removing Lock Overhead Using the Owners' Temporal Locality. 255-266
  
• Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz:
  The Stream Virtual Machine. 267-277
  
• Hao Yu, Dongmin Zhang, Lawrence Rauchwerger:
  An Adaptive Algorithm Selection Framework. 278-289