| * | 2009 |
| 47 | EE | Tobias Koal,
Daniel Scheit,
Heinrich Theodor Vierhaus:
A scheme of logic self repair including local interconnects.
DDECS 2009: 8-11 |
| 2008 |
| 46 | EE | Heinrich Theodor Vierhaus,
René Kothe:
Embedded Diagnostic Logic Test Exploiting Regularity.
DSD 2008: 873-879 |
| 45 | EE | Silvio Misera,
Heinrich Theodor Vierhaus,
André Sieber:
Simulated fault injections and their acceleration in SystemC.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 270-278 (2008) |
| 2007 |
| 44 | | René Kothe,
Heinrich Theodor Vierhaus:
Flip-Flops and Scan-Path Elements for Nanoelectronics.
DDECS 2007: 307-312 |
| 43 | EE | Heinrich Theodor Vierhaus,
Helmut Rossmann,
Silvio Misera:
Timing- / Power-Optimization for Digital Logic Based on Standard Cells.
DSD 2007: 303-306 |
| 42 | EE | Silvio Misera,
Heinrich Theodor Vierhaus,
André Sieber:
Fault Injection Techniques and their Accelerated Simulation in SystemC.
DSD 2007: 587-595 |
| 41 | EE | R. Frost Brandenburg,
D. Rudolph,
Christian Galke,
René Kothe,
Heinrich Theodor Vierhaus:
A Configurable Modular Test Processor and Scan Controller Architecture.
IOLTS 2007: 277-284 |
| 2006 |
| 40 | | Christian Galke,
René Kothe,
Heinrich Theodor Vierhaus:
Logic Self Repair.
ARCS Workshops 2006: 36-44 |
| 39 | EE | Udo Krautz,
Matthias Pflanz,
Christian Jacobi,
Hans-Werner Tast,
Kai Weber,
Heinrich Theodor Vierhaus:
Evaluating coverage of error detection logic for soft errors using formal methods.
DATE 2006: 176-181 |
| 38 | | René Kothe,
Christian Galke,
S. Schultke,
H. Froeschke,
S. Gaede,
Heinrich Theodor Vierhaus:
Hardware/Software Based Hierarchical Self Test for SoCs.
DDECS 2006: 159-160 |
| 37 | | René Kothe,
Heinrich Theodor Vierhaus,
Torsten Coym,
Wolfgang Vermeiren,
Bernd Straube:
Embedded Self Repair by Transistor and Gate Level Reconfiguration.
DDECS 2006: 210-215 |
| 36 | EE | Silvio Misera,
Heinrich Theodor Vierhaus,
Lars Breitenfeld,
André Sieber:
A Mixed Language Fault Simulation of VHDL and SystemC.
DSD 2006: 275-279 |
| 35 | EE | Christian Galke,
U. Gätzschmann,
Heinrich Theodor Vierhaus:
Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes.
DSD 2006: 433-438 |
| 34 | EE | Christian Galke,
René Kothe,
S. Schultke,
K. Winkler,
J. Honko,
Heinrich Theodor Vierhaus:
Embedded Scan Test with Diagnostic Features for Self-Testing SoCs.
IOLTS 2006: 181-182 |
| 33 | EE | S. Habermann,
René Kothe,
Heinrich Theodor Vierhaus:
Built-in Self Repair by Reconfiguration of FPGAs.
IOLTS 2006: 187-188 |
| 2005 |
| 32 | | Heinrich Theodor Vierhaus,
Helmut Rossmann:
Power-/Timing - Optimierung für Zellen-basierte Digitalschaltungen in Submikron-Technologien.
GI Jahrestagung (1) 2005: 339-343 |
| 31 | EE | René Kothe,
Christian Galke,
Heinrich Theodor Vierhaus:
A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features.
IOLTS 2005: 241-246 |
| 30 | EE | Marcin Gomulkiewicz,
Miroslaw Kutylowski,
Heinrich Theodor Vierhaus,
Pawel Wlaz:
Synchronization Fault Cryptanalysis for Breaking A5/1.
WEA 2005: 415-427 |
| 2004 |
| 29 | EE | Claudia Kretzschmar,
Christian Galke,
Heinrich Theodor Vierhaus:
A Hierarchical Self Test Scheme for SoCs.
IOLTS 2004: 37-44 |
| 28 | EE | Silvio Misera,
Heinrich Theodor Vierhaus:
FIT - A Parallel Hierarchical Fault Simulation Environment.
PARELEC 2004: 289-294 |
| 2003 |
| 27 | EE | Matthias Pflanz,
Heinrich Theodor Vierhaus:
Control Signal Protection For High Performance Processors.
IOLTS 2003: 173- |
| 26 | EE | Christian Galke,
Marcus Grabow,
Heinrich Theodor Vierhaus:
Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip.
IOLTS 2003: 183- |
| 25 | EE | Matthias Pflanz,
K. Walther,
Christian Galke,
Heinrich Theodor Vierhaus:
On-Line Techniques for Error Detection and Correction in Processor Registers with Cross-Parity Check.
J. Electronic Testing 19(5): 501-510 (2003) |
| 2002 |
| 24 | EE | Christian Galke,
Matthias Pflanz,
Heinrich Theodor Vierhaus:
A Test Processor Concept for Systems-on-a-Chip.
ICCD 2002: 210- |
| 23 | EE | Christian Galke,
Matthias Pflanz,
Heinrich Theodor Vierhaus:
On-line Detection and Compensation of Transient Errors in Processor Pipeline-Structures.
IOLTW 2002: 178 |
| 22 | EE | Matthias Pflanz,
K. Walther,
Christian Galke,
Heinrich Theodor Vierhaus:
On-Line Error Detection and Correction in Storage Elements with Cross-Parity Check.
IOLTW 2002: 69-73 |
| 2001 |
| 21 | EE | C. Rousselle,
Matthias Pflanz,
A. Behling,
T. Mohaupt,
Heinrich Theodor Vierhaus:
A register-transfer-level fault simulator for permanent and transient faults in embedded processors.
DATE 2001: 811 |
| 20 | EE | Matthias Pflanz,
K. Walther,
Heinrich Theodor Vierhaus:
On-line Error Detection Techniques for Dependable Embedded Processors with High Complexity.
IOLTW 2001: 51-53 |
| 19 | EE | Matthias Pflanz,
Heinrich Theodor Vierhaus:
Online Check and Recovery Techniques for Dependable Embedded Processors.
IEEE Micro 21(5): 24-40 (2001) |
| 1999 |
| 18 | | Matthias Pflanz,
Heinrich Theodor Vierhaus,
F. Pompsch:
An efficient on-line-test and back-up scheme for embedded processors.
ITC 1999: 964-972 |
| 17 | EE | Fulvio Corno,
Uwe Gläser,
Paolo Prinetto,
Matteo Sonza Reorda,
Heinrich Theodor Vierhaus,
Massimo Violante:
SymFony: a hybrid topological-symbolic ATPG exploiting RT-level information.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 191-202 (1999) |
| 1997 |
| 16 | EE | H.-Ch. Dahmen,
Uwe Gläser,
Heinrich Theodor Vierhaus:
An Efficient Dynamic Parallel Approach to Automatic Test Pattern Generation.
Great Lakes Symposium on VLSI 1997: 112-117 |
| 15 | | H.-Ch. Dahmen,
Uwe Gläser,
Heinrich Theodor Vierhaus:
A Parallel Approach Solving the Test Generation Problem for Synchronous Sequential Circuits.
PARCO 1997: 549-556 |
| 14 | EE | Uwe Hübner,
Heinrich Theodor Vierhaus,
Raul Camposano:
Partitioning and analysis of static digital CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1292-1310 (1997) |
| 1996 |
| 13 | EE | Jörg Wilberg,
A. Kuth,
Raul Camposano,
Wolfgang Rosenstiel,
Heinrich Theodor Vierhaus:
A Design Exploration Environment.
Great Lakes Symposium on VLSI 1996: 77-80 |
| 12 | | H.-Ch. Dahmen,
Uwe Gläser,
Heinrich Theodor Vierhaus:
Automatic Test Pattern Generation with Optimal Load Balancing.
PVM 1996: 205-212 |
| 11 | EE | Uwe Gläser,
Heinrich Theodor Vierhaus:
Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(4): 410-423 (1996) |
| 1995 |
| 10 | EE | Uwe Gläser,
Heinrich Theodor Vierhaus:
FOGBUSTER: an efficient algorithm for sequential test generation.
EURO-DAC 1995: 230-235 |
| 9 | EE | Fulvio Corno,
Paolo Prinetto,
Matteo Sonza Reorda,
Uwe Gläser,
Heinrich Theodor Vierhaus:
Improving topological ATPG with symbolic techniques.
VTS 1995: 338-343 |
| 1994 |
| 8 | | Michel Langevin,
Eduard Cerny,
Jörg Wilberg,
Heinrich Theodor Vierhaus:
Local microcode generation in system design.
Code Generation for Embedded Processors 1994: 171-187 |
| 7 | EE | Uwe Gläser,
Heinrich Theodor Vierhaus,
M. Kley,
A. Wiederhold:
Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation.
ICCAD 1994: 36-39 |
| 6 | | R. Wolber,
Uwe Gläser,
Heinrich Theodor Vierhaus:
Testability Analysis for Test Generation in Synchronous Sequential Circuits.
ICCD 1994: 350-353 |
| 1993 |
| 5 | | Heinrich Theodor Vierhaus,
Wolfgang Meyer,
Uwe Gläser:
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects.
ITC 1993: 83-91 |
| 4 | EE | Heinrich Theodor Vierhaus,
Wolfgang Meyer,
Uwe Gläser,
Raul Camposano:
Fault behavior and testability of asynchronous CMOS circuits.
Microprocessing and Microprogramming 38(1-5): 223-228 (1993) |
| 1992 |
| 3 | EE | Uwe Hübner,
Heinrich Theodor Vierhaus:
Efficient partitioning and analysis of digital CMOS-circuits.
ICCAD 1992: 280-283 |
| 2 | | Ursula Westerholz,
Heinrich Theodor Vierhaus:
Library Mapping of CMOS-Switch-Level-Circuits by Extraction of Isomorphic Subgraphs.
ICCD 1992: 472-475 |
| 1 | | Uwe Gläser,
Uwe Hübner,
Heinrich Theodor Vierhaus:
Mixed Level Hierarchical Test Generation for Transition Faults and Overcurrent Related Defects.
ITC 1992: 21-29 |