| |
| * | 2008 | |
|---|---|---|
| 3 | EE | Yu Hu, Victor Shih, Rupak Majumdar, Lei He: FPGA area reduction by multi-output function based sequential resynthesis. DAC 2008: 24-29 |
| 2 | EE | Yu Hu, Victor Shih, Rupak Majumdar, Lei He: Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1751-1760 (2008) |
| 2007 | ||
| 1 | EE | Yu Hu, Victor Shih, Rupak Majumdar, Lei He: Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. ICCAD 2007: 350-353 |
| 1 | Lei He | [1] [2] [3] |
| 2 | Yu Hu | [1] [2] [3] |
| 3 | Rupak Majumdar | [1] [2] [3] |