| * | 2009 |
|---|
| 7 | EE | Michael Pellauer,
Michael Adler,
Derek Chiou,
Joel S. Emer:
Soft connections: addressing the hardware-design modularity problem.
DAC 2009: 276-281 |
| 2008 |
|---|
| 6 | EE | Michael Pellauer,
Muralidaran Vijayaraghavan,
Michael Adler,
Arvind,
Joel S. Emer:
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.
FPGA 2008: 87-96 |
| 5 | EE | Michael Pellauer,
Muralidaran Vijayaraghavan,
Michael Adler,
Arvind,
Joel S. Emer:
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.
ISPASS 2008: 1-10 |
| 2007 |
|---|
| 4 | EE | Nirav Dave,
Arvind,
Michael Pellauer:
Scheduling as Rule Composition.
MEMOCODE 2007: 51-60 |
| 3 | EE | Nirav Dave,
Kermin Fleming,
Myron King,
Michael Pellauer,
Muralidaran Vijayaraghavan:
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA.
MEMOCODE 2007: 97-100 |
| 2006 |
|---|
| 2 | EE | Nirav Dave,
Michael Pellauer,
S. Gerding,
Arvind:
802.11a transmitter: a case study in microarchitectural exploration.
MEMOCODE 2006: 59-68 |
| 2005 |
|---|
| 1 | EE | Michael Pellauer,
Mieszko Lis,
Don Baltus,
Rishiyur S. Nikhil:
Synthesis of synchronous assertions with guarded atomic actions.
MEMOCODE 2005: 15-24 |
