| * | 2009 |
|---|
| 10 | EE | Pao-Ann Hsiung,
Chao-Sheng Lin,
Shang-Wei Lin,
Yean-Ru Chen,
Chun-Hsien Lu,
Sheng-Ya Tong,
Wan-Ting Su,
Chihhsiong Shih,
Chorng-Shiuh Koong,
Nien-Lin Hsueh,
Chih-Hung Chang,
William C. Chu:
VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development.
ICA3PP 2009: 303-314 |
| 9 | EE | Pao-Ann Hsiung,
Shang-Wei Lin,
Yean-Ru Chen,
Chun-Hsian Huang,
Chihhsiong Shih,
William C. Chu:
Modeling and verification of real-time embedded systems with urgency.
Journal of Systems and Software 82(10): 1627-1641 (2009) |
| 2007 |
|---|
| 8 | EE | Pao-Ann Hsiung,
Shang-Wei Lin,
Chin-Chieh Hung,
Jih-Ming Fu,
Chao-Sheng Lin,
Cheng-Chi Chiang,
Kuo-Cheng Chiang,
Chun-Hsien Lu,
Pin-Hsien Lu:
Real-Time Embedded Software Design for Mobile and Ubiquitous Systems.
EUC 2007: 718-729 |
| 7 | EE | Pao-Ann Hsiung,
Shang-Wei Lin:
From ISA to application design via RTOS— a course design framework for embedded software.
ICPADS 2007: 1-6 |
| 2006 |
|---|
| 6 | EE | Pao-Ann Hsiung,
Shang-Wei Lin,
Yean-Ru Chen,
Chun-Hsian Huang,
Jia-Jen Yeh,
Hong-Yu Sun,
Chao-Sheng Lin,
Hsiao-Win Liao:
Model Checking Timed Systems with Urgencies.
ATVA 2006: 67-81 |
| 2005 |
|---|
| 5 | EE | Shang-Wei Lin,
Pao-Ann Hsiung,
Chun-Hsian Huang,
Yean-Ru Chen:
Model Checking Prioritized Timed Automata.
ATVA 2005: 370-384 |
| 4 | EE | Pao-Ann Hsiung,
Shang-Wei Lin:
Model Checking Timed Systems with Priorities.
RTCSA 2005: 539-544 |
| 2004 |
|---|
| 3 | EE | Pao-Ann Hsiung,
Shang-Wei Lin:
Formal Design and Verification of Real-Time Embedded Software.
APLAS 2004: 382-397 |
| 2 | EE | Pao-Ann Hsiung,
Shang-Wei Lin:
Automatic Synthesis and Verification of Real-Time Embedded Software.
EUC 2004: 12-21 |
| 1 | EE | Pao-Ann Hsiung,
Shang-Wei Lin,
Chih-Hao Tseng,
Trong-Yen Lee,
Jih-Ming Fu,
Win-Bin See:
VERTAF: An Application Framework for the Design and Verification of Embedded Real-Time Software.
IEEE Trans. Software Eng. 30(10): 656-674 (2004) |
